A FIFO (First In First Out) memory, referred to here as a synchronous FIFO, is a FIFO whose data input and data output ports both operate synchronously using the same clock signal. The synchronous FIFO memory is usually referred to just simply as a “synchronous FIFO”. Such a synchronous FIFO generally receives a push control signal and an input data value on its data input port. If the push signal is adequately set up on a push signal input lead of the FIFO, and if the data value is adequately set up on a set of data input leads of the FIFO, then on the next rising edge of the clock signal the data value is captured into the FIFO. This operation is referred to as pushing. The external circuit that supplies the push signal to the FIFO and that supplies the data value to the FIFO is generally being clocked synchronously by the same clock signal. The external circuit initiates the assertion of the push signal and the supplying of the data value to the FIFO in response to a rising edge of the clock signal at the beginning of a prior clock cycle, so the external circuitry must therefore be fast enough to supply the push and data input values to the FIFO input port in less than one clock cycle so that the push and data value signals are present on the input port in adequate time before the next rising edge of the same clock signal. If the setup time requirements of the FIFO are large, then there is only a relatively smaller amount of time available for the external circuitry to supply the push and data values. This is undesirable and limits overall circuit operating speed.
Similarly, from the perspective of the output port of the FIFO, there is also external circuitry that launches the pop signal and that receives the data value from the FIFO in return. This external circuitry generally initiates the assertion of the pop signal in response to a rising edge of the clock signal. Moreover, the external circuitry is clocked by the clock signal and may need to capture the resulting data value as output by the FIFO upon the next rising edge of the clock signal. If signal propagation delays within the FIFO are such that the pop signal has relatively large setup time requirements, then relatively less time is left for the external circuitry to supply to pop signal to the FIFO. In addition, if signal propagation delays within the FIFO are such that it takes the FIFO a relatively large amount of time to output the data value following the initiating rising edge of the clock signal, then relatively less time is available for the external circuitry to conduct the data value from the FIFO to the external latch or register before the next rising edge of the clock signal occurs. If the pop setup time of the FIFO is large and/or if the clock-to-data output propagation delay of the FIFO is large, then the operating speed of the overall circuit may be undesirably low.